Write VHDL code to realize half-adder

Aim : Write VHDL code to realize half-adder

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity half_adder is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           s : out  STD_LOGIC;

           c : out  STD_LOGIC);

end half_adder;

architecture Behavioral of half_adder is

begin

process(a,b)

begin

if (a='0' and b='0') then

            s<='0';

            c<='0';

elsif (a='0' and b='1') then

            s<='1';

            c<='0';

elsif (a='1' and b='0') then

            s<='1';

            c<='0';

elsif (a='1' and b='1') then

            s<='0';

            c<='1';

else

            null;

end if;

end process;

end Behavioral;