Write VHDL code for 0-99 counter

Aim : Write VHDL code for 0-99 counter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updown is

    Port ( clk : in  STD_LOGIC;

           up_down : in  STD_LOGIC;

           count : out integer range 0 to 127);

end updown;

architecture Behavioral of updown is

begin

process(clk)

 variable cnt:integer range 0 to 127;

 constant modulus:integer:=99;

begin

if (clk'event and clk='1') then

if up_down='1' then

if cnt=modulus then

cnt:=0;

else

cnt:=cnt+1;

end if;

else

if cnt=0 then

cnt:=modulus;

else

cnt:=cnt-1;

end if;

end if;

end if;

count<=cnt;

end process;

end Behavioral;