Write VHDL code for making 8:3 priority encoder

Aim : Write VHDL code for making 8:3 priority encoder.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity priority_encoder_8_3 is

    Port ( a : in  STD_LOGIC_VECTOR(7 downto 0);

           b : out  STD_LOGIC_VECTOR(2 downto 0));

end priority_encoder_8_3;

architecture Behavioral of priority_encoder_8_3 is

begin

process(a)

begin

            if a(0)='1' then b<="000";

elsif a(1)='1' then b<="001";

elsif a(2)='1' then b<="010";

elsif a(3)='1' then b<="011";

elsif a(4)='1' then b<="100";

elsif a(5)='1' then b<="101";

elsif a(6)='1' then b<="110";

elsif a(7)='1' then b<="111";

else null;

end if;

end process;