Write VHDL code to realize Full subtractor

Aim : Write VHDL code to realize Full subtractor.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity full_subtractor is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : in  STD_LOGIC;

           d : out  STD_LOGIC;

           borrow : out  STD_LOGIC);

end full_subtractor;

architecture Behavioral of full_subtractor is

begin

d<=a xor b xor c;

borrow<=(c and (not(a xor b)))or ((not a) and b);

end Behavioral;