Write VHDL code for making XOR gate using structural modeling using NAND gate.

Aim: Write VHDL code for making XOR gate using structural modeling using NAND gate.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity xor_using_nand is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           x : out  STD_LOGIC);

end xor_using_nand;

architecture Behavioral of xor_using_nand is

component nand_gate

port(a,b:in std_logic;

c:out std_logic);

end component;

signal s0,s1,s2:std_logic;

begin

x1:nand_gate port map(a,b,s0);

x2:nand_gate port map(a,s0,s1);

x3:nand_gate port map(b,s0,s2);

x4:nand_gate port map(s1,s2,x);

end Behavioral;