Write VHDL code for binary to gray convertor

Aim : Write VHDL code for binary to gray convertor.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bintogray is

    Port ( Bin : in  STD_LOGIC_VECTOR(3 downto 0);

           Gray : out  STD_LOGIC_VECTOR(3 downto 0));

end bintogray;

architecture Behavioral of bintogray is

begin

Gray <= "0000" when Bin = "0000" else

        "0001" when Bin = "0001" else

                          "0011" when Bin = "0010" else

                          "0010" when Bin = "0011" else

                          "0110" when Bin = "0100" else

                          "0111" when Bin = "0101" else

                          "0101" when Bin = "0110" else

                          "0100" when Bin = "0111" else

                          "1100" when Bin = "1000" else

                          "1101" when Bin = "1001" else

                          "1111" when Bin = "1010" else

                          "1110" when Bin = "1011" else

                          "1010" when Bin = "1100" else

                          "1011" when Bin = "1101" else

                          "1001" when Bin = "1110" else

                          "1000" when Bin = "1111" ;

end Behavioral;