Write VHDL code for universal shift register

Aim : Write VHDL code for universal shift register.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity uni_shift is

    Port ( din : in  STD_LOGIC_VECTOR(7 downto 0);

           clk : in  STD_LOGIC;

           load : in  STD_LOGIC;

           dout : out  STD_LOGIC_VECTOR(7 downto 0));

end uni_shift;

architecture Behavioral of uni_shift is

begin

process(clk)

begin

if(clk='1' and clk'event)then

dout<=din;

end if;

end process;

end Behavioral;