Write VHDL code to realize full-adder

Write VHDL code to realize full-adder.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity full_adder is

    Port ( an : in  STD_LOGIC;

           bn : in  STD_LOGIC;

           cn : in  STD_LOGIC;

           sum : out  STD_LOGIC;

           carry : out  STD_LOGIC);

end full_adder;

architecture Behavioral of full_adder is

signal z: STD_LOGIC_VECTOR(2 downto 0);

begin

process(an,bn,cn)

begin

z<=an & bn & cn;

case (z) is

when "000"=>

            sum<='0';

            carry<='0';

when "001"=>

            sum<='1';

            carry<='0';

when "010"=>

            sum<='1';

            carry<='0';

when "011"=>

            sum<='0';

            carry<='1';

when "100"=>

            sum<='1';

            carry<='0';

when "101"=>

            sum<='0';

            carry<='1';

when "110"=>

            sum<='0';

            carry<='1';

when "111"=>

            sum<='1';

            carry<='1';

when others=>

            null;

end case;

end process;

end Behavioral;