Write VHDL code to realize Binary to BCD converter

Aim : Write VHDL code to realize Binary to BCD converter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bintobcd is

    Port ( Bin : in  STD_LOGIC_VECTOR(3 downto 0);

           BCD : out  STD_LOGIC_VECTOR(4 downto 0));

end bintobcd;

architecture Behavioral of bintobcd is

begin

process(bin)

begin

if(Bin="0000")then

   BCD<="00000";

elsif(Bin="0001")then

   BCD<="00001";

elsif(Bin="0010")then

   BCD<="00010";

elsif(Bin="0011")then

   BCD<="00011";

elsif(Bin="0100")then

   BCD<="00100";

elsif(Bin="0101")then

   BCD<="00101";

elsif(Bin="0110")then

   BCD<="00110";

elsif(Bin="0111")then

   BCD<="00111";

elsif(Bin="1000")then

   BCD<="01000";

elsif(Bin="1001")then

   BCD<="01001";

elsif(Bin="1010")then

   BCD<="10000";

elsif(Bin="1011")then

   BCD<="10001";

elsif(Bin="1100")then

   BCD<="10010";

elsif(Bin="1101")then

   BCD<="10011";

elsif(Bin="1110")then

   BCD<="10100";

elsif(Bin="1111")then

   BCD<="10101";

end if;

end process;

end Behavioral;