Write VHDL code for shift left/shift right register

Aim : Write VHDL code for shift left/shift right register.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity shift_reg is

    Port ( din : in  STD_LOGIC;

           clr : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           Q : out  STD_LOGIC);

end shift_reg;

architecture Behavioral of shift_reg is

signal temp: std_logic_vector(7 downto 0);

begin

process (clk,clr)

begin

if(clr='1') then

temp <=(others=>'0');

elsif (clk'event and clk='1')then

temp <=temp(6 downto 0)& din;

end if;

end process;

Q<=temp(7);

end Behavioral;