Write VHDL code for making 2:1 multiplexer using structural modelling

Aim : Write VHDL code for making 2:1 multiplexer using structural modelling

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux_2_1 is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : in  STD_LOGIC;

           z : out  STD_LOGIC);

end mux_2_1;

architecture Behavioral of mux_2_1 is

component and1

port(a,b:in std_logic;

c:out std_logic);

end component;

component not1

port(a:in std_logic;

b:out std_logic);

end component;

component or1

port(a,b:in std_logic;

c:out std_logic);

end component;

signal s0,s1,s2:std_logic;

begin

x1:not1 port map(c,s0);

x2:and1 port map(a,c,s1);

x3:and1 port map(b,c,s2);

x4:or1 port map(s1,s2,z);

end Behavioral;