Write VHDL code for baud rate

Aim : Write VHDL code for baud rate.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity baud_rate is

    generic (

    N: integer := 8;

    M: integer :=163);

    Port (clk, reset : in  STD_LOGIC;

           tick : out  STD_LOGIC;

              q : out STD_LOGIC_VECTOR(N-1 downto 0));

end baud_rate;

architecture Behavioral of baud_rate is

signal r_reg :  unsigned(N-1 downto 0);

signal r_next : unsigned(N-1 downto 0);

begin

process(clk,reset)

begin

    if (reset ='1') then

        r_reg <= (others=>'0');

    elsif(clk'event and clk='1') then

    r_reg <= r_next;

    end if;

end process;

r_next <= (others =>'0') when r_reg=(M-1) else r_reg+1;

tick <='1' when r_reg=(M-1) else '0';

q <= std_logic_vector(r_reg);

end Behavioral;