Write VHDL code for 2’s compliment

Aim : Write VHDL code for 2’s compliment.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity com2s is

    Port ( din : in  STD_LOGIC_VECTOR(7 downto 0);

           dout : out  STD_LOGIC_VECTOR(7 downto 0));

end com2s;

architecture Behavioral of com2s is

begin

dout <= not(din) + "00000001";

end Behavioral;