Write VHDL code for Johnson Counter

Aim : Write VHDL code for Johnson Counter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity john_count is

    Port ( clk, rst: in  STD_LOGIC;

           Q : inout unsigned(3 downto 0));

end john_count;

architecture Behavioral of john_count is

signal temp : unsigned(3 downto 0);

begin

Q <= temp;

process(clk)

begin

if( rising_edge(clk) ) then

if (rst = '1') then

temp <= (others => '0');

else

temp(1) <= temp(0);

temp(2) <= temp(1);

temp(3) <= temp(2);

temp(0) <= not temp(3);

end if;

end if;

end process;

end Behavioral;