Write VHDL code for different kinds of flip flops

Aim : Write VHDL code for different kinds of flip flops.

(a)   JK flip flop

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkff1 is

    Port ( j : in  STD_LOGIC;

           k : in  STD_LOGIC;

           clr : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           q : out  STD_LOGIC;

           w : out  STD_LOGIC);

end jkff1;

architecture seq of jkff1 is

signal y:std_logic;

begin

process (j,k,clk,clr)

begin

if clr='0' then y<='0';

elsif clk'event and clk='0' then

if j='1' and k='1' then

y<=not y;

elsif j='0' and k='1' then

y<='0';

elsif j='1' and k='0' then

y<='1';

else null;

end if;

end if;

end process;

q<= y;

w<= not y;

end seq;

(a)    D-flip flop

library IEEE;

use IEEE.std_logic_1164.all;

entity d_ff_srss is

port (

d,clk,reset,set : in STD_LOGIC;

q : out STD_LOGIC);

end d_ff_srss;

architecture d_ff_srss of d_ff_srss is

begin

process(clk)

begin

if clk'event and clk='1' then

if reset='1' then

q <= '0';

elsif set='1' then

q <= '1';

else

q <= d;

end if;

end if;

end process;

end d_ff_srss;

(c)SR flip-flop

library IEEE;

use IEEE.std_logic_1164.all;

entity d_ff_aras is

port (

d,clk,reset,set : in STD_LOGIC;

q : out STD_LOGIC);

end d_ff_aras;

architecture d_ff_aras of d_ff_aras is

begin

process(clk,reset,set)

begin

if reset='1' then

q <= '0';

elsif set='1' then

q <= '1';

elsif clk'event and clk='1' then

q <= d;

end if;

end process;

end d_ff_aras;