Write VHDL code for baud rate

Aim : Write VHDL code for baud rate.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity baud_rate is

    generic (

    N: integer := 8;

    M: integer :=163);

    Port (clk, reset : in  STD_LOGIC;

           tick : out  STD_LOGIC;

              q : out STD_LOGIC_VECTOR(N-1 downto 0));

end baud_rate;

architecture Behavioral of baud_rate is

signal r_reg :  unsigned(N-1 downto 0);

signal r_next : unsigned(N-1 downto 0);

begin

process(clk,reset)

begin

    if (reset ='1') then

        r_reg <= (others=>'0');

    elsif(clk'event and clk='1') then

    r_reg <= r_next;

    end if;

end process;

r_next <= (others =>'0') when r_reg=(M-1) else r_reg+1;

tick <='1' when r_reg=(M-1) else '0';

q <= std_logic_vector(r_reg);

end Behavioral;

Write VHDL code for 0-99 counter

Aim : Write VHDL code for 0-99 counter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updown is

    Port ( clk : in  STD_LOGIC;

           up_down : in  STD_LOGIC;

           count : out integer range 0 to 127);

end updown;

architecture Behavioral of updown is

begin

process(clk)

 variable cnt:integer range 0 to 127;

 constant modulus:integer:=99;

begin

if (clk'event and clk='1') then

if up_down='1' then

if cnt=modulus then

cnt:=0;

else

cnt:=cnt+1;

end if;

else

if cnt=0 then

cnt:=modulus;

else

cnt:=cnt-1;

end if;

end if;

end if;

count<=cnt;

end process;

end Behavioral;

Write VHDL code for universal shift register

Aim : Write VHDL code for universal shift register.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity uni_shift is

    Port ( din : in  STD_LOGIC_VECTOR(7 downto 0);

           clk : in  STD_LOGIC;

           load : in  STD_LOGIC;

           dout : out  STD_LOGIC_VECTOR(7 downto 0));

end uni_shift;

architecture Behavioral of uni_shift is

begin

process(clk)

begin

if(clk='1' and clk'event)then

dout<=din;

end if;

end process;

end Behavioral;

Write VHDL code for Johnson Counter

Aim : Write VHDL code for Johnson Counter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity john_count is

    Port ( clk, rst: in  STD_LOGIC;

           Q : inout unsigned(3 downto 0));

end john_count;

architecture Behavioral of john_count is

signal temp : unsigned(3 downto 0);

begin

Q <= temp;

process(clk)

begin

if( rising_edge(clk) ) then

if (rst = '1') then

temp <= (others => '0');

else

temp(1) <= temp(0);

temp(2) <= temp(1);

temp(3) <= temp(2);

temp(0) <= not temp(3);

end if;

end if;

end process;

end Behavioral;

Write VHDL code for shift left/shift right register

Aim : Write VHDL code for shift left/shift right register.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity shift_reg is

    Port ( din : in  STD_LOGIC;

           clr : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           Q : out  STD_LOGIC);

end shift_reg;

architecture Behavioral of shift_reg is

signal temp: std_logic_vector(7 downto 0);

begin

process (clk,clr)

begin

if(clr='1') then

temp <=(others=>'0');

elsif (clk'event and clk='1')then

temp <=temp(6 downto 0)& din;

end if;

end process;

Q<=temp(7);

end Behavioral;

Write VHDL code for different kinds of flip flops

Aim : Write VHDL code for different kinds of flip flops.

(a)   JK flip flop

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkff1 is

    Port ( j : in  STD_LOGIC;

           k : in  STD_LOGIC;

           clr : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           q : out  STD_LOGIC;

           w : out  STD_LOGIC);

end jkff1;

architecture seq of jkff1 is

signal y:std_logic;

begin

process (j,k,clk,clr)

begin

if clr='0' then y<='0';

elsif clk'event and clk='0' then

if j='1' and k='1' then

y<=not y;

elsif j='0' and k='1' then

y<='0';

elsif j='1' and k='0' then

y<='1';

else null;

end if;

end if;

end process;

q<= y;

w<= not y;

end seq;

(a)    D-flip flop

library IEEE;

use IEEE.std_logic_1164.all;

entity d_ff_srss is

port (

d,clk,reset,set : in STD_LOGIC;

q : out STD_LOGIC);

end d_ff_srss;

architecture d_ff_srss of d_ff_srss is

begin

process(clk)

begin

if clk'event and clk='1' then

if reset='1' then

q <= '0';

elsif set='1' then

q <= '1';

else

q <= d;

end if;

end if;

end process;

end d_ff_srss;

(c)SR flip-flop

library IEEE;

use IEEE.std_logic_1164.all;

entity d_ff_aras is

port (

d,clk,reset,set : in STD_LOGIC;

q : out STD_LOGIC);

end d_ff_aras;

architecture d_ff_aras of d_ff_aras is

begin

process(clk,reset,set)

begin

if reset='1' then

q <= '0';

elsif set='1' then

q <= '1';

elsif clk'event and clk='1' then

q <= d;

end if;

end process;

end d_ff_aras;

Write VHDL code for 2’s compliment

Aim : Write VHDL code for 2’s compliment.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity com2s is

    Port ( din : in  STD_LOGIC_VECTOR(7 downto 0);

           dout : out  STD_LOGIC_VECTOR(7 downto 0));

end com2s;

architecture Behavioral of com2s is

begin

dout <= not(din) + "00000001";

end Behavioral;

Write VHDL code to realize Binary to BCD converter

Aim : Write VHDL code to realize Binary to BCD converter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bintobcd is

    Port ( Bin : in  STD_LOGIC_VECTOR(3 downto 0);

           BCD : out  STD_LOGIC_VECTOR(4 downto 0));

end bintobcd;

architecture Behavioral of bintobcd is

begin

process(bin)

begin

if(Bin="0000")then

   BCD<="00000";

elsif(Bin="0001")then

   BCD<="00001";

elsif(Bin="0010")then

   BCD<="00010";

elsif(Bin="0011")then

   BCD<="00011";

elsif(Bin="0100")then

   BCD<="00100";

elsif(Bin="0101")then

   BCD<="00101";

elsif(Bin="0110")then

   BCD<="00110";

elsif(Bin="0111")then

   BCD<="00111";

elsif(Bin="1000")then

   BCD<="01000";

elsif(Bin="1001")then

   BCD<="01001";

elsif(Bin="1010")then

   BCD<="10000";

elsif(Bin="1011")then

   BCD<="10001";

elsif(Bin="1100")then

   BCD<="10010";

elsif(Bin="1101")then

   BCD<="10011";

elsif(Bin="1110")then

   BCD<="10100";

elsif(Bin="1111")then

   BCD<="10101";

end if;

end process;

end Behavioral;

Write VHDL code for binary to gray convertor

Aim : Write VHDL code for binary to gray convertor.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bintogray is

    Port ( Bin : in  STD_LOGIC_VECTOR(3 downto 0);

           Gray : out  STD_LOGIC_VECTOR(3 downto 0));

end bintogray;

architecture Behavioral of bintogray is

begin

Gray <= "0000" when Bin = "0000" else

        "0001" when Bin = "0001" else

                          "0011" when Bin = "0010" else

                          "0010" when Bin = "0011" else

                          "0110" when Bin = "0100" else

                          "0111" when Bin = "0101" else

                          "0101" when Bin = "0110" else

                          "0100" when Bin = "0111" else

                          "1100" when Bin = "1000" else

                          "1101" when Bin = "1001" else

                          "1111" when Bin = "1010" else

                          "1110" when Bin = "1011" else

                          "1010" when Bin = "1100" else

                          "1011" when Bin = "1101" else

                          "1001" when Bin = "1110" else

                          "1000" when Bin = "1111" ;

end Behavioral;

Write VHDL code for 8 bit parity generator (with for loop and generic stat events)

Aim : Write VHDL code for 8 bit parity generator (with for loop and generic stat events).

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pairity is

generic(n:integer:=7);

port(a:in std_logic_vector(n-1 downto 0);

b:out std_logic_vector(n downto 0));

end pairity;

architecture Behavioral of pairity is

begin

process(a)

            variable temp1:std_logic;

            variable temp2:std_logic_vector(b'range);

            begin

                        temp1:='0';

                        for i in a'range loop

                                    temp1:=temp1 xor a(i);

                                    temp2(i):=a(i);

                        end loop;

                                    temp2(b'high):=temp1;

                                    b<=temp2;

end process;

end Behavioral;

Write VHDL code for making 8:3 priority encoder

Aim : Write VHDL code for making 8:3 priority encoder.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity priority_encoder_8_3 is

    Port ( a : in  STD_LOGIC_VECTOR(7 downto 0);

           b : out  STD_LOGIC_VECTOR(2 downto 0));

end priority_encoder_8_3;

architecture Behavioral of priority_encoder_8_3 is

begin

process(a)

begin

            if a(0)='1' then b<="000";

elsif a(1)='1' then b<="001";

elsif a(2)='1' then b<="010";

elsif a(3)='1' then b<="011";

elsif a(4)='1' then b<="100";

elsif a(5)='1' then b<="101";

elsif a(6)='1' then b<="110";

elsif a(7)='1' then b<="111";

else null;

end if;

end process;    

Write VHDL code for making 2:1 multiplexer using structural modelling

Aim : Write VHDL code for making 2:1 multiplexer using structural modelling

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux_2_1 is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : in  STD_LOGIC;

           z : out  STD_LOGIC);

end mux_2_1;

architecture Behavioral of mux_2_1 is

component and1

port(a,b:in std_logic;

c:out std_logic);

end component;

component not1

port(a:in std_logic;

b:out std_logic);

end component;

component or1

port(a,b:in std_logic;

c:out std_logic);

end component;

signal s0,s1,s2:std_logic;

begin

x1:not1 port map(c,s0);

x2:and1 port map(a,c,s1);

x3:and1 port map(b,c,s2);

x4:or1 port map(s1,s2,z);

end Behavioral;

Write VHDL code to realize Full subtractor

Aim : Write VHDL code to realize Full subtractor.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity full_subtractor is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : in  STD_LOGIC;

           d : out  STD_LOGIC;

           borrow : out  STD_LOGIC);

end full_subtractor;

architecture Behavioral of full_subtractor is

begin

d<=a xor b xor c;

borrow<=(c and (not(a xor b)))or ((not a) and b);

end Behavioral;

Write VHDL code to realize Half-subtractor

Aim : Write VHDL code to realize Half-subtractor

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity half_subtractor is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           di : out  STD_LOGIC;

           bo : out  STD_LOGIC);

end half_subtractor;

architecture Behavioral of half_subtractor is

begin

process(a,b)

begin

if (a='0' and b='0') then

            di<='0';

            bo<='0';

elsif (a='0' and b='1') then

            di<='1';

            bo<='1';

elsif (a='1' and b='0') then

            di<='1';

            bo<='0';

elsif (a='1' and b='1') then

            di<='0';

            bo<='0';

else

            null;

end if;

end process;

end Behavioral;