Write VHDL code for baud rate

Aim : Write VHDL code for baud rate.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity baud_rate is

    generic (

    N: integer := 8;

    M: integer :=163);

    Port (clk, reset : in  STD_LOGIC;

           tick : out  STD_LOGIC;

              q : out STD_LOGIC_VECTOR(N-1 downto 0));

end baud_rate;

architecture Behavioral of baud_rate is

signal r_reg :  unsigned(N-1 downto 0);

signal r_next : unsigned(N-1 downto 0);

begin

process(clk,reset)

begin

    if (reset ='1') then

        r_reg <= (others=>'0');

    elsif(clk'event and clk='1') then

    r_reg <= r_next;

    end if;

end process;

r_next <= (others =>'0') when r_reg=(M-1) else r_reg+1;

tick <='1' when r_reg=(M-1) else '0';

q <= std_logic_vector(r_reg);

end Behavioral;

Write VHDL code for 0-99 counter

Aim : Write VHDL code for 0-99 counter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updown is

    Port ( clk : in  STD_LOGIC;

           up_down : in  STD_LOGIC;

           count : out integer range 0 to 127);

end updown;

architecture Behavioral of updown is

begin

process(clk)

 variable cnt:integer range 0 to 127;

 constant modulus:integer:=99;

begin

if (clk'event and clk='1') then

if up_down='1' then

if cnt=modulus then

cnt:=0;

else

cnt:=cnt+1;

end if;

else

if cnt=0 then

cnt:=modulus;

else

cnt:=cnt-1;

end if;

end if;

end if;

count<=cnt;

end process;

end Behavioral;

Write VHDL code for universal shift register

Aim : Write VHDL code for universal shift register.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity uni_shift is

    Port ( din : in  STD_LOGIC_VECTOR(7 downto 0);

           clk : in  STD_LOGIC;

           load : in  STD_LOGIC;

           dout : out  STD_LOGIC_VECTOR(7 downto 0));

end uni_shift;

architecture Behavioral of uni_shift is

begin

process(clk)

begin

if(clk='1' and clk'event)then

dout<=din;

end if;

end process;

end Behavioral;

Write VHDL code for Johnson Counter

Aim : Write VHDL code for Johnson Counter.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity john_count is

    Port ( clk, rst: in  STD_LOGIC;

           Q : inout unsigned(3 downto 0));

end john_count;

architecture Behavioral of john_count is

signal temp : unsigned(3 downto 0);

begin

Q <= temp;

process(clk)

begin

if( rising_edge(clk) ) then

if (rst = '1') then

temp <= (others => '0');

else

temp(1) <= temp(0);

temp(2) <= temp(1);

temp(3) <= temp(2);

temp(0) <= not temp(3);

end if;

end if;

end process;

end Behavioral;

Write VHDL code for shift left/shift right register

Aim : Write VHDL code for shift left/shift right register.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity shift_reg is

    Port ( din : in  STD_LOGIC;

           clr : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           Q : out  STD_LOGIC);

end shift_reg;

architecture Behavioral of shift_reg is

signal temp: std_logic_vector(7 downto 0);

begin

process (clk,clr)

begin

if(clr='1') then

temp <=(others=>'0');

elsif (clk'event and clk='1')then

temp <=temp(6 downto 0)& din;

end if;

end process;

Q<=temp(7);

end Behavioral;

Write VHDL code for different kinds of flip flops

Aim : Write VHDL code for different kinds of flip flops.

(a)   JK flip flop

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkff1 is

    Port ( j : in  STD_LOGIC;

           k : in  STD_LOGIC;

           clr : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           q : out  STD_LOGIC;

           w : out  STD_LOGIC);

end jkff1;

architecture seq of jkff1 is

signal y:std_logic;

begin

process (j,k,clk,clr)

begin

if clr='0' then y<='0';

elsif clk'event and clk='0' then

if j='1' and k='1' then

y<=not y;

elsif j='0' and k='1' then

y<='0';

elsif j='1' and k='0' then

y<='1';

else null;

end if;

end if;

end process;

q<= y;

w<= not y;

end seq;

(a)    D-flip flop

library IEEE;

use IEEE.std_logic_1164.all;

entity d_ff_srss is

port (

d,clk,reset,set : in STD_LOGIC;

q : out STD_LOGIC);

end d_ff_srss;

architecture d_ff_srss of d_ff_srss is

begin

process(clk)

begin

if clk'event and clk='1' then

if reset='1' then

q <= '0';

elsif set='1' then

q <= '1';

else

q <= d;

end if;

end if;

end process;

end d_ff_srss;

(c)SR flip-flop

library IEEE;

use IEEE.std_logic_1164.all;

entity d_ff_aras is

port (

d,clk,reset,set : in STD_LOGIC;

q : out STD_LOGIC);

end d_ff_aras;

architecture d_ff_aras of d_ff_aras is

begin

process(clk,reset,set)

begin

if reset='1' then

q <= '0';

elsif set='1' then

q <= '1';

elsif clk'event and clk='1' then

q <= d;

end if;

end process;

end d_ff_aras;

Write VHDL code for 2’s compliment

Aim : Write VHDL code for 2’s compliment.

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity com2s is

    Port ( din : in  STD_LOGIC_VECTOR(7 downto 0);

           dout : out  STD_LOGIC_VECTOR(7 downto 0));

end com2s;

architecture Behavioral of com2s is

begin

dout <= not(din) + "00000001";

end Behavioral;